Erfan Gholami
All projects

ARM 8 Processor Implementation

A pipelined ARM processor in Verilog — fetch to write-back, simulated and verified in ModelSim.

2017Shahid Beheshti University
Verilog · HDL · Computer Architecture

Computer Architecture ends the only way it honestly can: build the processor. The final project at Shahid Beheshti was an ARM 8 pipeline, written in Verilog and proven in simulation.

What it covers

  • The five classic stages — fetch, decode, execute, memory, write-back — implemented as a working pipeline
  • Simulated and verified in ModelSim, instruction by instruction, waveform by waveform

Years later this is still the project I credit for how I read Android: once you have watched instructions move through a pipeline you built, no layer of the stack is a black box.

All projectsWork with meWritten from the repository, not the résumé.