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2017·Shahid Beheshti University·University
ARM 8 Processor Implementation
Pipelined ARM 8 processor implemented in Verilog as a Computer Architecture project.
VerilogHDLComputer ArchitectureModelsim
Implemented a pipelined ARM 8 processor as a Computer Architecture final project at Shahid Beheshti University.
- —Full pipeline implementation using Verilog HDL
- —Simulated and verified with Modelsim
- —Covers fetch, decode, execute, memory, and write-back stages